SAN JOSE, Calif. — Achronix Semiconductor Corp. (San Jose) is using asynchronous circuitry to deliver a 1.5 GHz FPGA now sampling. The startup hopes to use its three-fold lead in data rates to grab ASICs sockets in high-end communications, test and other systems beyond the reach of existing parts from Altera, Xilinx and others.
Whether Achronix can deliver on the promise of its technology remains to be seen. It is lining up a suite of tools and silicon intellectual property for its part which it says will be in production in the first half of 2009.
The new 65 nm device represents a second attempt at a commercial product. About a year ago, the company killed its so-called Ultra chip--a 90 nm, 1.93 GHz version announced in 2006, saying it lacked the mix of features users wanted.
"Assuming they can deliver, they would be filling a void that's existed for quite awhile, providing a new top end for the FPGA market," said Rich Wawrzyniak, an analyst with Semico Research (Phoenix). "There's always been a pretty wide gap between the top end of ASICs and FPGAs."
"It's certainly a viable approach to take," said David Greenfield, senior director of product marketing for high-end FPGAs at Altera, speaking of a move to faster data rates. "We have looked at it before and will continue to look at it," he said.
Altera decided to build more dense products rather than faster ones with its 40 nm chips set to ship later this year. The new Stratix parts will have the same native speeds of about 350 MHz of its existing 65 nm chips, but the new chips will double to as many as 700,000 the number of logic elements. They will support hard cores running at up to 550 MHz.
"There are multiple ways to address performance in the critical path for any particular design, sometimes it's through the clock and sometimes its elsewhere," said Greenfield. Only about ten percent of customers for Altera's Hard Copy FPGA-to-ASIC service are seeking its 30-50 percent higher data rates, he added.
The Achronix SPD60 is built up from relatively conventional four-input look up tables (LUTs) encapsulated in a 1.5 GHz synchronous logic. Inside that frame the chip employs routing elements made up from basic transmit and receive components that use asynchronous acknowledgements rather than clock cycles to stage the flow of data.
The approach allows higher throughput than traditional flip-flops that gate logic elements in traditional FPGAs. It emerged from research in asynchronous logic by two company founders--Rajit Manohar, an associate professor at the School of Electrical and Computer Engineering at Cornell University and one of his doctoral students, Clint Kelly.
The company is one of a growing group of startups—including 10 Gbit switch designer Fulcrum Microsystems--tapping asynchronous logic to leapfrog traditional devices.
"Other FPGAs have to deal with a big global clock that needs to be distributed, skewed and balanced--that fundamentally limits performance," claimed John Lofton Holt, chief executive and co-founder of the company.
The startup envisions a family of four Speedster chips all running at up to 1.5 GHz and supporting up to four 1,066 MHz DDR3 memory controllers. The initial SPD60 includes 47,000 look-up tables and can hold up to 20 10.3 Gbit serdes licensed from the former Snowbush Microelectronics.
Achronix plans to follow up the part with a high end SPD180 with 163,000 LUTs and room for twice as many 10G serdes. A low end part will have two memory controllers, 24,000 LUTs and fit in a 31x31 mm package. The devices will range widely in price and power consumption from $200 and less than 20 W to $2,500 and more than 40 W.
Holt claims the family can address a $1.7 billion slice of the ASIC market that traditional FPGAs cannot reach. "We can become a billion-dollar company without winning a single existing Xilinx or Altera socket," Holt said.
Achronix had announced in 2006 its 1.93 GHz Ultra chip built in a 90 nm process at Chartered Semiconductor. But the startup soon found it lacked features prospective users demanded and consumed more power than they would tolerate.
