By using this innovative design, the researchers at imec and Holst Centre have realized a 6.4 MS/s 13 bit ADC in 40nm CMOS. Thanks to the low-power calibration, this ADC achieves an effective number of bits (or ENOB) of 10.4 bit and a state-of-the-art power-efficiency of 5.5 fJ per conversion step at 6.4 MS/s. Overall, the chip consumes 46 µW from a 1 V supply. The ADC achieves 64.1 dB SNDR (or signal-to noise and distortion ratio). In combination with the ENOB, this gives a good indication of the overall dynamic performance of the ADC. When compared to similar work, our ADC achieves the best power efficiency, while also integrating, on chip, a background calibration technique for comparator offset and DAC mismatch.
Figure ADC results: Performance summary and comparison with state-of-the-art. Click image to enlarge.
What’s in it for industrial partners?
Imec and Holst Centre’s SAR ADC is available for interested parties through IP licensing. For more information, visit www2.imec.be/be_en/research/wireless-communication/ultralow-power-wireless-communic.html.