Custom designed wireless links: what the 2012 VLSI Symposia had on offer : Page 2 of 3

September 05, 2012 // By Julien Happich
Sponsored by the electron devices Society, the Solid State Circuits Society and the Japan Society of Applied Physics, the 2012 VLSI Symposia which took place last summer in Honolulu came as an opportunity for researchers to unveil new short-range wireless links and design concepts. Striking examples include inductive RF coupling solutions for in-chip communications or through-skull neural sensing data collection.
3D-chip levels, instead of silicon vias. Designed as part of the digital CMOS circuit integration, this solution is claimed to be less expensive than using through silicon vias (TSVs) while offering similar bandwidth. The researchers listed various issues with TSVs, including their excessive footprint or the open failures they cause due to thermal stress. They looked at near-field communication at 50 GHz in the 1 mm range.

Figure 3: ThruChip interface (TCI): (a-top) inductive coupling, (b-bottom) coil by multi-layer wires.

The ThruChip Interface is described as being surge-tolerant, thermally resilient, while imposing no restrictions on the circuit position within multi-layer stacks. This multi-layer interconnection is said to require only 3% of the footprint of conventional CMOS I/Os. It was tested with stacks of 128 dies, supporting a data rate per coil of 11 Gb/s/ch and aggregating a data rate of 8 Tb/s by arranging 1000 channels within 6.4mm 2 while drawing two orders of magnitude less power than conventional high-speed memory links such as DDR.

This inter-chip, intra-stack communication technology could find use not only in large memory stacks that make up solid-state drives but also for multiple processor packages or for non-contact wafer-level testing as well as for debugging by probing internal bus data wirelessly through a device’s package.

A student in the Department of Electrical Engineering at the National Tsing Hua University in Taiwan, Chang-Ming Lai presented an ultra-wideband (UWB) impulse radio timed-array radar implemented in 0.18 μm CMOS technology.

Using a time-shifted direct-sampling architecture, the 4-channel transmitter array generates and sends a variety of 10GS/s pulses towards targets while the receiver array samples the reflected signal in RF domain directly by time interleaved sampling at 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC).

According to the student, the proposed architecture has range and azimuth resolution of 0.75

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