The ThruChip Interface is described as being surge-tolerant, thermally resilient, while imposing no restrictions on the circuit position within multi-layer stacks. This multi-layer interconnection is said to require only 3% of the footprint of conventional CMOS I/Os. It was tested with stacks of 128 dies, supporting a data rate per coil of 11 Gb/s/ch and aggregating a data rate of 8 Tb/s by arranging 1000 channels within 6.4mm 2 while drawing two orders of magnitude less power than conventional high-speed memory links such as DDR.
This inter-chip, intra-stack communication technology could find use not only in large memory stacks that make up solid-state drives but also for multiple processor packages or for non-contact wafer-level testing as well as for debugging by probing internal bus data wirelessly through a device’s package.
A student in the Department of Electrical Engineering at the National Tsing Hua University in Taiwan, Chang-Ming Lai presented an ultra-wideband (UWB) impulse radio timed-array radar implemented in 0.18 μm CMOS technology.
Using a time-shifted direct-sampling architecture, the 4-channel transmitter array generates and sends a variety of 10GS/s pulses towards targets while the receiver array samples the reflected signal in RF domain directly by time interleaved sampling at 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC).
According to the student, the proposed architecture has range and azimuth resolution of 0.75