Proof of concept
A composite test signal consisting of (1) a TM3.1, 20 MHz LTE carrier centered at 300 MHz, and (2) a 253.44 MHz, -35 dBFS calibration sine-wave, corresponding to S=1, K=8, P=2K, can be generated using the test setup shown in Figure 3.
Figure 3: Block diagram of the test setup. Click image to enlarge.
This setup provides very high dynamic range thanks to low noise and high linearity D/A converter  and DVGA . A commercially available 14-bits / 500-Msps TIADC that integrates high resolution tunable gain and timing errors is used. The ADC raw data was captured with an FPGA and processed with IDT’s calibration algorithm using Matlab® software. The gain and timing errors of the TIADC have been set to approximately 0.5 dB and 5 ps respectively to simulate a worst case situation.