Real-time calibration of gain and timing errors in two-channel time-interleaved A/D converters for SDR applications: Page 4 of 6

June 25, 2014 // By Djamel Haddadi, Integrated Device Technology, Inc.
The explosion of mobile data is driving new receiver architectures in communication infrastructure in order to provide higher capacity and more flexibility.
Once estimated, the gain and timing errors are used to feed a digital correction engine. The gain is compensated using a simple digital multiplier. The correction of the timing error is accomplished with a modified fractional delay filter [3]. Polyphase and symmetry are exploited to reduce the implementation complexity of the filter. Both the estimation and correction engines operate at the sub-ADC sampling rate. Down-sampling can be envisioned for the estimation block for further optimization.

Proof of concept

A composite test signal consisting of (1) a TM3.1, 20 MHz LTE carrier centered at 300 MHz, and (2) a 253.44 MHz, -35 dBFS calibration sine-wave, corresponding to  S=1, K=8, P=2K,  can be generated using the test setup shown in Figure 3.

Figure 3: Block diagram of the test setup. Click image to enlarge.

This setup provides very high dynamic range thanks to low noise and high linearity D/A converter [4] and DVGA [5]. A commercially available 14-bits / 500-Msps TIADC that integrates high resolution tunable gain and timing errors is used. The ADC raw data was captured with an FPGA and processed with IDT’s calibration algorithm using Matlab® software. The gain and timing errors of the TIADC have been set to approximately 0.5 dB and 5 ps respectively to simulate a worst case situation.

Design category: 

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