Real-time calibration of gain and timing errors in two-channel time-interleaved A/D converters for SDR applications: Page 6 of 6

June 25, 2014 //By Djamel Haddadi, Integrated Device Technology, Inc.
The explosion of mobile data is driving new receiver architectures in communication infrastructure in order to provide higher capacity and more flexibility.
Conclusion

RF sampling A/D converters are key components for next generation software defined radio systems. Time-interleaved architecture is leveraged to achieve very high sampling rates and low power consumption at the cost of degraded dynamic range. It has been shown that injecting a constrained calibration signal out of the useful band improves significantly this dynamic range thanks to a low complexity calibration algorithm for gain and timing errors. Measurements on 14/500 Msps prototype showed an approximate 30 dB dynamic range improvement across the two first Nyquist zones. The proposed method can be used for higher-speed applications as long as the gain/timing mismatch error model remains valid.

References

  1. Jiangfeng Wu et al., “A 5.4Gsps 12b 500mW Pipeline ADC in 28nm CMOS”, 2013 Symposium on VLSI Circuits Digest of Technical Papers.
  2. Vogel, C.; Johansson, H., “Time-interleaved analog-to-digital converters: status and future directions,” ISCAS, May 2006.
  3. Laakso, T.I.; Valimaki, V.; Karjalainen, M.; Laine, U.K., “Splitting the unit delay,” Signal Processing Magazine, IEEE , vol.13, no.1, pp.30,60, Jan 1996
  4. IDTDAC1653D datasheet: http://www.idt.com/document/dst/dac1653d-dac1658d-datasheet
  5. IDTF1241 datasheet: http://www.idt.com/document/dst/f1241-datasheet

The author, Djamel Haddadi holds the post of Technical Leader - RF, High Speed Data Converters at IDT, www.idt.com.

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