Wireless applications: OS consideration for Zynq All Programmable SoCs: Page 4 of 5

April 15, 2015 // By Yuan Gu, Xilinx
With the explosive increase in wireless data throughput, there is tremendous pressure on improving digital signaling processing technology and radio equipment. Currently, the focus is on 4G LTE.
Selecting the appropriate architecture for supporting both the DPD application and control processing application is highly important as it will define the overall performance, reliability, and ease of maintenance.

A common architecture selected for wireless radio application is AMP mode. This devotes a full ARM core to DPD processing when it is running in bare metal mode and provides more computing head room to meet time requirement of DPD coefficient updates. All other applications such as control and OAM run on the second OS controlled ARM A9 core. In this architecture, since the OS only has control of one of two ARM cores, an inter-processor channel has to be established between the applications in the two separate cores, such as using the OCM (On Chip Memory) or shared memory. This is especially important for some key control applications, for example, the application for monitoring the DPD module health. Such Inter-Process Communication (IPC) solutions are none standard and have to be developed separately in the AMP mode.

The SMP architecture is very straightforward with a single OS instance controlling both ARM cores and thus all applications. IPC, debugging and the supporting tool chain are all under the same OS. In order to ensure resources are devoted to DPD application, specific techniques such as core affinity and interrupt shielding can be applied in the software application. In the former case, the DPD application will be running on one core only, potentially no other tasks sharing resources (other than OS scheduler overhead). In the latter case, interrupt services (other than those triggered by the DPD application) are directed to the second core. Thus resources are fully utilized by the DPD application.

Based on the facts stated above, the Zynq APSoC is the ideal platform to support either AMP or SMP architecture. As shown in Figure 3, Zynq integrates two ARM core processors, 12.5 Gb/s SerDes and 500 MHz+ DSP with higher reliability, and provides whole digital front-end functionality such as DPD, CFR, DUC/DDC and CPRI/JESD interfaces. This solution removes the need for interfaces between the processors and separate FPGA, simplifies the PCB design.

Figure 3: Migration from discrete system to Zynq. Click image to enlarge.

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