Implementing the equations for Class-E plus the device’s losses inside the harmonic balance (Figure 9), we obtained the following results (Figures 10 and 11).
From simulation, we got an efficiency of 93.4% and a power out of 512 W at 13.56 MHz (Figure 12). Using two SD4933 in parallel, we have halved the RDS(on) and the stray inductances, but we doubled the equivalent capacitance Coss.
At this point of the design, the nonlinear characteristic of the Coss versus the drain voltage was under particular consideration.
To depower the negative effects of Coss, we introduced the advantages offered by the finite feed inductor already introduced.