Industry is responding by developing variants of the Doherty power amplifier (DPA) architecture, which already combines high efficiency with limited design complexity and cost.
The Doherty architecture, first proposed in 1936 , is traditionally seen as a narrowband solution. Recent publications have proposed DPAs with greater bandwidth, but many of them are either complex for example requiring input drive conditioning ; of limited power output (less than 100 W)  ; or only suitable for sub-GHz applications .
Building a better Doherty amplifier
We have already developed  a variant of the DPA, called an integrated DPA (iDPA) architecture, which operates from 1.805 to 2.17 GHz, and reaches 47% efficiency at 6 dB back-off (that is, 6 dB less than peak operating power). Unfortunately, this design’s symmetric topology means that its efficiency drops off rapidly when used at greater levels of back-off. This is a drawback, since the complex modulation schemes used in 4G networks create signals with high peak-to-average power ratios (PAPR), which means base-station power amplifiers often need to operate with 8 to 16 dB of back-off.
To counter this issue we have developed a four-way iDPA topology that offers multi-band capability and good efficiency when operated with a lot of back-off.
The conventional output-matching scheme for the discrete power transistors of a Doherty amplifier works by resonating the drain-to-source parasitic capacitor CDS with a shunt inductance. This approach works, but limits the amplifier’s fractional bandwidth (a measure of its wideband capabilities) to a maximum of 10%.
In a symmetric iDPA topology, the drain-to-source parasitic capacitance CDS is absorbed in a broadband manner, using an equivalent transmission line suitable for Doherty operation (see Figure 1). This allows up to 28% of fractional bandwidth.