Realizing 5G and IoT RF systems with off-the-shelf components: Page 4 of 5

June 29, 2017 //By How-Siang Yap, Keysight Technologies, Inc.
Architecting and building RF systems for 5th Generation (5G) and Internet-of-Things (IoT) applications to achieve the best performance at the lowest cost and in the shortest time places intense pressure on the engineers who are tasked to do the work. This article explains how the process can be performed efficiently through accurate RF system simulation with real off-the-shelf components and fast multi-stage impedance matching synthesis on a printed circuit board layout.

Designing for the Internet of Things

Multiple standards are emerging for IoT radios based on range of coverage, data bandwidth, and operating frequencies. The IoT frequencies can be broadly divided into 2 categories: Sub 1 GHz, and those above, namely around the 2.4 GHz and 5.8 GHz ISM (Industrial, Scientific and Medical) bands. From the perspective of designing IoT physical radio links that work at these frequency bands, the main focus should be on impedance matching the IoT chipset to the antenna. For a longer range, amplifiers may be inserted in between the chipset and the antenna.

Ideally, the impedance matching network has to be compact and economical to build. Multistage impedance matching over a broad bandwidth (30% or more) to complex frequency-dependent impedances such as an antenna; measured S-parameters of an IoT chipset; or an unstable non-unilateral discrete transistor amplifier is extremely difficult and tedious using traditional Smith chart or benchtop cut-and-try techniques.

A more efficient and optimal approach is the use of automatic impedance matching synthesis, which employs multiple algorithms from simple L-sections to the Real-Frequency-Technique, for addressing the increasingly difficult above-mentioned impedance matching problems. Because synthesis can accomplish difficult simultaneous multi-stage matching in seconds with distributed and/or lumped networks, the IoT radio designer can quickly experiment with multiple matching topologies to select one that is most economical to build. Figure 5 shows the result of 3-stage, simultaneous matching of an antenna to a low-noise stabilized transistor amplifier circuit, followed by the measured S-parameter of a chipset power amplifier to achieve -20 dB return loss match from 2 to 3 GHz and a gain of 35 dB. The microstrip layout dimensions were also synthesized with the automatic insertion of discontinuities such as tees and open stubs. The entire process was completed within one hour.  


Figure 5:  Impedance matching synthesis and microstrip layout of 3 stage matching network from 2 to 3 GHz to achieve -20 dB return loss and 35 dB gain is done in < 1 hour.

 

Design category: