Intuitive design tools
The FPRF design tools feature user-friendly and intuitive graphical user interfaces (GUI). The GUI allows full access to all the programmable features, so that different settings can be downloaded in real time. These settings include receive path, transmit path, digital signal processing (DSP) characteristics and I/O configurations. The settings are directly loaded from the PC to provide an instant update to the performance. Once the optimum solution is found, the settings are saved to a file for production programming. The flexibility of the FPRF makes it the ideal component for a software defined radio.
The analogue components on FPRF devices are not the only programmable parts. There can be extensive user programmable DSP blocks dispersed throughout some chips in both receive and transmit paths. For example, in the receiver, the programmable analogue filtering is supplemented by digital filtering to produce a combined enhanced filter function with reduced distortion. The DSP also provides digital frequency synthesis and mixer functions, enabling the IF frequency to be shifted to any desired value within the bandwidth of the on-chip data converters. Therefore, designers can experiment with direct conversion, low and high IF transceiver architectures for their wireless application.
Highly flexible RF design options
The FPRFs have been designed to comply with the requirements for most cellular, commercial and military applications. However, users are not restricted to an “all or nothing” use of the device. On some devices, major blocks can be bypassed or disabled in favour of an external solution (Figure 5). If the on-chip 12-bit ADC provides insufficient resolution, then designers can use an external device. The analogue signals from the baseband gain block are available at pins, and the unused ADCs can be powered-down. There are options to use external filters and to bypass and power-down the on-chip filters. Alternatively, if the system only requires the use of particular elements within the chip, the user can power down the rest of the circuitry. This is similar to the concept of FPGAs where the end user can engage any number of digital building blocks to perform various functions.