Mixel provided the D-PHY IP Rx+ hard macro for the NXP design. This macro is optimized as a receive-side custom implementation that efficiently fronts the CSI-2 interface in the system-level chip, S32V. It’s noteworthy that the MIPI D-PHY specification defines a universal form of the D-PHY with symmetrical Tx and Rx capabilities.
In Mixel’s implementation, the receive side is targeted and the lanes are optimized to align with the major transfer direction from the camera to the S32V. The block diagram of the Mixel D-PHY Rx+ is shown in Figure 4. A key feature in the Rx+ is the area optimized Tx side. Adding a minimally invasive Tx adds loopback support and eases the set up required in a post silicon production test. Not only do you get performance and power, but silicon testability as a result of this special implementation.
Mixel’s D-PHY Rx+ follows the MIPI D-PHY specification but adds this important custom option. Note that the MIPI Alliance defines its specifications to allow optimizations during implementation. In this way, customers and vendors can work within the pin limit constraints and data rate transfer requirements of the system, optimizing for power and efficiency, and in this case, also testability.
Safety and reliability
Certainly, operational reliability and robustness are fundamental to the parts used in automobiles. Because ADAS features are mission critical for making us safer as we drive, safety standards are essential. But even non-critical systems must operate reliably across a wide, and often severe, range of environmental conditions.