A design with two power-combined 8 x 150µm transistors was developed. Allowing for the losses of the on-chip biasing and matching networks, this would still allow the target 6W (37.7 dBm) minimum output power requirement to be exceeded.
Further detailed load-pull simulations were then undertaken on the selected transistor. The power delivered to the load at 4-dB compression was plotted against PAE at 10 GHz for a range of load impedances. Each trace in the resulting plot in Figure 2 represents a constant real part of the load impedance with a varying imaginary part. This analysis was used to select the optimum load impedance of 11.25 + j21.67Ω that was used as the target during the design process. Analysis of the optimum load impedance at the 2nd and 3rd harmonics was also undertaken and accounted for during the detailed circuit design.
The design approach was to power-combine the RF outputs of two of the selected transistors. Throughout the design process, effort was expended on ensuring that the die area was minimized. This can be clearly seen from the layout plot reproduced in Figure 3(a).
Duplicate on-chip drain biasing networks are included at top and bottom of the IC. This preserves symmetry and allows the PA to be biased from either side. The transmission line used to provide the drain bias is also used as inductive matching at the drain of each transistor to allow the optimum inductive load impedance to be presented to the transistor as well as ensuring that the 2nd and 3rd harmonic terminations are favourably located.