High impedance series lines are used at each transistor output to transform the common 50Ω load impedance at the output of the PA to the lower impedance that is required at the drains of the transistors. This is in order to present the optimum real part of the load at each transistor output.
The input matching network is a low-pass structure that transforms the low impedance at the transistors’ input to a 50Ω impedance at the PA input. On-chip balancing resistors are included between the two PA channels to ensure odd-mode stability. On-chip RC de-coupling is included at both gate and drain to ensure low frequency stability where the GaN transistors have a very high level of available gain.
Realisation and Measured Performance
A photograph of one of the PA die is shown in Figure 3(b). The die measures just 1.5-mm x 2-mm, which means that a single 4” diameter wafer should contain around 2300 amplifier ICs.
The s-parameters of 40 amplifiers measured on wafer at a bias of 25V Vds and 90mA Ids were measured and plotted. The small signal gain was measured as 14 dB at 9 GHz, dropping to 12.1 dB at 11 GHz.