ADI's MS-DPD (mixed-signal, digital pre-distortion) development platform simplifies the wireless infrastructure design process by allowing OEMs to quickly assess and reprogram the radio to remove non-linearities from the transmit paths and enhance radio power efficiency.

ADI's MS-DPD platform incorporates a high-performance RF and mixed-signal transmit and observation receiver chain supporting 2G, 3G and emerging 4G wireless protocols. Xilinx's Virtex-6 FPGA ML605 (field-programmable gate array) Evaluation Kit connects to the MS-DPD board through an industry-standard VITA-57 FMC connector. Using this system, the FPGA can be used to implement required radio algorithms leveraging the ADI signal chain available on the MS-DPD.

"In collaboration with Xilinx, customers now have everything needed to demonstrate the transmit section of a base station radio," said Martin Cotter, segment director, Communications Infrastructure, Analog Devices. "ADI has combined high performance transceiver components into a single development platform for speeding the evaluation of critical DPD algorithms running on Xilinx's Virtex-6 ML605 Evaluation Kit. The MS-DPD platform allows our customers to focus on differentiating their DPD algorithm from their competitors' solutions."

Claiming the highest dynamic performance in its class, the multi-carrier MS-DPD development platform simplifies component selection and board layout to make it easier for designers of multi-carrier GSM and multi-standard SDR (software-defined radio) base stations to develop FPGA-based DPD algorithms. FPGAs also provide the flexibility to optimize the solution that competing fixed-function ASICs (application-specific integrated circuits) cannot, while providing a highly integrated, low cost, low power and high reliability solution to present day base station needs.

"In collaborating with Analog Devices, we have been able to create a more modular approach to radio development, leveraging the new industry-standard FMC connectors," said Manuel Uhm, director, Wireless Communications Business, Xilinx. "Customers are able to rapidly evaluate Xilinx's crest factor reduction (CFR) and DPD algorithms in conjunction with ADI's high-performance transmitter solutions, saving considerable engineering time. Furthermore, customers can leverage the Virtex-6 ML605 FPGA Evaluation Kit and MS-DPD to develop and evaluate their own IP."

ADI's MS-DPD development board includes more than 12 Analog Devices RF and mixed-signal components, including the recently announced AD9122 1.2-GSPS DAC and ADL5375 quadrature modulator, in addition to amplifiers, mixers, clock ICs, power management ICs, and PLL circuits. The observation path includes the AD9230 12-bit, 250-MSPS ADC to maximize the bandwidth available for DPD.

For further information: www.xilinx.com/ml605.