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Small signal and power performance of AlGaN/GaN HFETs grown on semi-insulating SiC This paper, by a A. Weiszt, R. Dietrich, J.S. Lee, A. Vescan, H. Leier, b E.L Pinar, c J.M. Redwing & d H. Sledzikc, won the prize for the best oral paper at GAAS 2000. It describes the performance of AlGaN/GaN HFETs grown on semi-insulating SiC substrate, showing a record transconductance of 300mS/mm for a device with a gate length of 0.3m and output power levels above 4W CW at 10GHz for an unpassivated 1.6mm device.
a
DaimlerChrysler AG, Research
and Technology, P.O. Box 2360, D-89013 Ulm, Germany, phone:+49-731-505-2087
email:
andreas.wieszt@daimlerchrysler.com
.
The high operating voltages, the high breakdown voltage, the saturation velocity of electrons in AlGaN/GaN heterostructures and the excellent thermal conductivity of SiC as a substrate material make GaN on SiC the right choice for future power amplifier and switching devices in a variety of military and commercial wireless communications applications. For example, it has been demonstrated that power densities at X-band are several times higher than GaAs based FETs [1]. This in turn correlates quite well with theoretical predicted power densities for AlGaN/GaN power FETs on SiC[2]. To develop a model of a high power amplifier, it is necessary to perform DC, pulsed, small signal, and large signal characterization of the FETs, from which the data to be used in an amplifier design is extracted. Technology The devices used for the characterization were fabricated on epitaxial
GaN layers, which were grown on semi-insulating. SiC in a horizontal MOCVD
reactor at 1100ýC. A 100nm AlN nucleation layer, a 2ým GaN buffer and
a top AlGaN barrier/ supply layer were deposited on the SiC. The AlGaN
structure consists
of a 3nm undoped spacer, a 10nm Si-doped (1x10
19
cm
-3
) supply and a 5nm undoped cap layer.
The Al-content is 25%. Device separation was performed by RIE in a BCl
3
/Ar atmosphere. Ohmic contacts were fabricated using a Ti/Al metallization
annealed in a N
2
ambient at 900ýC for 30s.
The contact resistance was characterized by the TLM method. The
measured
values are between 0.3 and 0.5mm
DC, RF and load pull measurements
After processing, the devices were analyzed by DC, RF and power measurements. The DC measurements showed for 2x50ým devices a maximum drain current (at V gs =+1V) of 1.5A/mm and a maximum transconductance of 300mS/mm at V ds =10V, which is one of the highest ever reported for this gatelength, shown in Figure 1. At higher V ds the output current and the transconductance are reduced due to self heating of the device. The self heating also becomes significant as the periphery of the FETs is increased. Hence, a reduced maximum current density and transconductance were recorded for large periphery devices, yielding 1.1A/mm and 210mS/mm respectively for the same bias point. Small signal measurements with the 100x0.3ým 2 device resulted in a ft of 40GHz and a f max of 78GHz. Additional RF measurements with a 1600x0.3ým 2 device led to a ft of 41GHz and a f max of 43GHz. These values are suitable for the design of high power amplifier at X- or Ku-band.
On-wafer load pull measurements were performed at 10GHz using a measurement setup with mechanical tuners. No harmonic termination was applied. The 1.6mm device yielded an output power of 36.5dBm, corresponding to a power density of 2.8W/mm, which is an excellent result for an unpassivated large periphery device. Higher output power levels could be expected by proper passivation of the surface [3]. The device was biased at V ds =25V and V gs =-4.5V leading to a drain current of 230mA (class AB) shown in Figure 4.The self biasing effect pushed the drain current up to almost 500mA. The PAE was approximately 32%. Higher drain-source-voltages could not yet be applied due to a limitation of the currently used DC power source currently being used. The break-down voltage of the device is around 70V. Small signal analysis
For large signal modelling of a power amplifier, knowledge of the small signal FET parameters was very helpful. To distinguish between extrinsic and intrinsic parameters several measurements were made. To extract the extrinsic parasitics of the devices, S-parameters at two different bias conditions were measured ( pinch-off and large forward gate-bias). For the intrinsic parameters several bias points in the linear and the saturation region were applied. The drain and source resistances were determined by DC measurements [6] and by the method of [4,5]. The resistances were extracted from the S-parameters measured for large forward gate bias and fitted to their proposed Z-parasitic topology model. The fitted values, which were evaluated with Agilent EEsof, were verified with DC measured values. The inductances were also extracted by this method. To separate parasitics, which belong exclusively to the pads and the parasitics of the FET itself, gate width dependent S-parameter measurements were performed. The pad geometry was kept unchanged and only the gate width of the FETs were varied. The derived equations of [4,5] were used to extract the extrinsic parameters of the S-parameters, which were also measured at pinch-off and large forward gate-bias. Afterwards they were plotted against gate width, and the pad parasitics were extrapolated for zero gate width. These values were used as extrinsic constants for the fitting of the intrinsic parameters.
Finally, the S-parameters of the linear and the saturation region of the IV-curve were fitted to a standard small signal equivalent circuit shown in Figure 2, for two different devices, one with the gate width of 100ým and the other with 1.6mm gate width. In Figure 3 the measured and the modelled S-parameters are shown for the smaller FET. The figure shows a good agreement between the measured and the modelled data, particularly in the frequency range of 1 to 25GHz. The modelled parameters of both FETs are listed in Table 1. The capacitances
Cgs, Cds, Cgd and the transconductance gm are normalized to 1mm. The capacitances
scale quite well with the
device size within a range of 10%-40% (intrinsic
area ratio: FET
large
/FET
small
=16). However, the resistive components and the transconductance behave
non-linearly with size, beyond experimental and/or fitting error, most
probably due increased self heating in the larger device. Using the data
from small signal equivalent circuit an extrinsic transconductance of
285mS/mm and 230mS/mm for the small
and for the large device can be calculated,
using gm
extrin
=gm
intrin
/(1+Rs*gm
intrin
), in good agreement with
the data extracted from DC measurements. For both fittings a source resistance
of around 0.5
Conclusion In conclusion, we fabricated small and large periphery devices on semi insulating SiC. DC characterization showed state of the art transconductance for a 100x0.3ým 2 device reflecting excellent material properties. S-parameter measurement yield an f t of 40GHz and f max of 78GHz for a 100ým device. Power measurements shows output power of >4W CW (2.8W/mm) for a unpassivated 1.6mm device at 10GHz. Small signal equivalent circuit parameters have been analyzed for two devices with different gatewidths indicating that a standard equivalent HEMT circuit can be taken to describe AlGaN/GaN HFETs. However, in order to use this approach to design large periphery devices, we will have to take into account the thermal behaviour of the device components, which do not scale linearly with device size. Acknowledgment The author wishes to thank Anton Schurr for performing RF measurements. References [1] Y.F.Wu, D. Kapolnek , N.-Q. Zhang, P. Parikh, B.P.
Keller and U.K. Mishra, High Al-Content AlGaN/GaN Hemts On SiC Substrates
With Very-high Power Performance, 1999, IEDM Tech. Dig., pp 925-927
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The 0.3ým T-shaped Ni gate was defined by e-beam lithography. For large
periphery devices, up to a gatewidth of 1.6mm, multi-finger structures
with 3ým Au airbridges were used.
