16nm FinFET analog ASIC integrates ADC/DAC for 5G

November 23, 2017 // By Peter Clarke
Japanese fabless chip company MegaChips Corp., has announced a 16nm FinFET analog ASIC that integrates a gigabit-class analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to create an analog front end (AFE) for 5G networks and other high-speed applications.

The analog ASIC provides a 14-bit, 3.4-Gsps/6.8-Gsps ADC and 12-bit, 3.4-Gsps/6.8-Gsps DAC—in a 16nm SoC that saves power, cost and space when compared to a circuit made of an FPGA and discrete ADCs.

The Analog Mega Block (AMB) intellectual property design includes ADCs, DACs, PGAs, IAMPs, PLLs and filters.

"Achieving compliance with today’s communications standards is a long and complicated process," said Masahiro Konishi, general manager of MegaChips. "We have a dedicated team of experts focused on AMB development. They work alongside our customers as a virtual R&D team, from the initial design specification through certification and production ramp up."

"MegaChips has a long track record of successfully delivering state-of-the-art high-speed ASICs for passive optical networks (PON), home networks (HPNA, G.hn), and access networks (G.fast)," commented Yuji Sakuma, general manager of MegaChips.

MegaChips previously added a 28nm AMB with 0.6-Gsps/1.2-Gsps, 14-bit ADC and DAC and a 65nm/130nm AMB with 200-Msps/400-Msps 12-bit ADC and DAC to its analog ASIC IP family.

www.megachips.co.jp/english