The company was formed in 2017 by Sang-Soo Lee, a former vice president of analog design at SuVolta Inc., and others. A paper on its approach prepared with researchers from the University of Minnesota, has been presented at the International Electron Devices Meeting being held in San Francisco. The paper is titled: "A 68 parallel row access neuromorphic core with 22K multi-level aynapses based on logic-compatible embedded flash memory technology."
The paper discusses a spiking neuromorphic core utilizing logic-compatible embedded flash technology for storing multi-level synaptic weights is demonstrated in a 65nm standard CMOS process. The memory supports reading of 5 levels, equivalent to 2.3 bits.
The chip features multi-level non-volatile weight storage, and single-cycle current integration and spike generation and can contain 320 neurons. The weights were tuned using a program-verify sequence, allowing 68 individual cell currents to be summed up simultaneously. Authors report that to their knowledge that is the highest number yet reported.
The 68 parallel-row design supports 22,000 multi-level synapses and these e-flash based synapses are non-volatile and therefore consume zero standby power and support instant on/off operation.
The test-chip was used for hand-written single digit recognition at which it achieved 91.8 percent accuracy, close to the 93.8 percent accuracy of a software model with the same number of weight levels. The paper states that the maximum throughput of the core is 1.28G pixels/s and the average power consumption of a single neuron circuit is 15.9 microwatts.
The company has announced that patent applications have been filed in US and other countries.