IBM Research Alliance develops process for 5nm chips

June 05, 2017 // By Jean-Pierre Joosting
Hot on the heels of a 7nm test node chip with 20 billion transistors developed less then two years ago, IBM and its Research Alliance partners GLOBALFOUNDRIES and Samsung, as well as equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5nm chips.

At 5nm, scientists have paved the way for 30 billion switches on a fingernail-sized chip that will deliver increased performance to accelerate cognitive computing, the IoT, and other data-intensive applications delivered in the cloud. Significant power savings at 5nm will also enable batteries in smartphones and other mobile products to last two to three times longer than today' between charges.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering's NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan.

"For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential," said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research. "That's why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems."

IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors manufactured using an industry-first process that can deliver 40 percent performance enhancement at fixed power.

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