Low power FPGA boasts 12.7 Gbps transceivers

February 22, 2017 //By Jean-Pierre Joosting
Microsemi Corporation and Silicon Creations have developed the industry's lowest power field programmable gate array (FPGA) with 12.7 Gbps transceivers, using a Serializer/Deserializer (SerDes) PHY from Silicon Creations.

These transceivers have been deployed on the latest ultralow power PolarFire™ mid-range FPGAs from Microsemi. The multiprotocol PHY helps ensure PolarFire FPGAs support a wide variety of serial protocols used for designs in the wireline access, wireless infrastructure and industry 4.0 markets.  

"Our collaboration with Silicon Creations to develop and integrate a highly innovative PHY technology with a rich physical coding sublayer has provided the FPGA industry with a highly compelling multiprotocol transceiver that will solve problems across multiple market segments, especially in wireline access and cellular infrastructure," said Lyle Smith, vice president of product development engineering for Microsemi's system-on-chip (SoC) business unit. "Silicon Creations was diligent in providing high quality verified PHY intellectual property on schedule, and provided critical signal integrity and integration support enabling Microsemi to deliver PolarFire silicon that met or exceeded target specifications on performance and power consumption."

PolarFire FPGAs have leveraged Silicon Creations' extensive portfolio of phase locked loop (PLL) and high-speed input/output (I/O) circuitry to develop SerDes IP. The PHY supports a range of different SerDes protocols, including Ethernet 10G-KR/R; PCIe Gen 1/2; common public radio interface (CPRI) rates 1 to 9; JESD204B; OIF-CEI 6G and 11G; SATA, Serial Digital Interface (SDI) and various standards around Passive Optical Networks (PON).

With total power for the PHYs as low as 4.5 mW/GB/lane that has resulted in the FPGA industry's lowest power 12.7 Gbps transceivers and output random jitter below 0.35ps RMS at 12.7 Gbps, make the PHYs suitable for transmitting data over OIF and IEEE802.3 compliant short- and long-reach channels at ultralow power. The PHY's ring PLL provides low area and continuous tuning range from 0.25 Gbps to 12.7 Gbps. The PLL also can operate in fractional-N mode that allows arbitrary frequency precision, precise spread-spectrum generation and jitter cleaning for applications such as 10G-KR or Synchronous Ethernet.