RISC-V based CPU core with Linux support ideal for AI, IoT and networking

October 05, 2017 //By Jean-Pierre Joosting
SiFive has announced the U54-MC Coreplex IP, which claims to be the first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux.

The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of the U54-MC Coreplex marks the architecture's expansion into the application processor space – opening entirely new use cases for RISC-V.

As the first RISC-V application processor capable of running embedded Linux, the standard U54-MC Coreplex contains four U54 CPUs along with a single E51 CPU, and is the first commercial RISC-V core to include multicore support and cache coherence. Each U54 CPU utilizes a highly efficient five-stage in-order pipeline. The U54 cores support the RV64GC ISA, which is expected to be the standard for Linux-based RISC-V devices. The 64-bit E51 CPU serves as a management core and is fully coherent with the main U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.

"SiFive has achieved another significant milestone for the RISC-V community," said Rick O'Connor, executive director of the non-profit RISC-V Foundation. "The ability for RISC-V developers to develop Linux and other Unix-based operating systems on commercial grade silicon will enable the RISC-V software ecosystem to quickly expand beyond embedded systems, and bring new solutions to market."

SiFive's U54-MC Coreplex has been taped out as part of SiFive's Freedom Unleashed family of high-performance, customizable RISC-V SoCs. As implemented in the Freedom Unleashed platform, the U54 and E51 CPUs run at 1.5+ GHz in 28nm technology. Each of the U54 CPUs implement a 32KB Instruction Cache and 32KB Data Cache, and all of the cores share a coherent, 2MB L2 Cache. Customers can license the U54-MC Coreplex in a variety of configurations besides the 4+1 default configuration.

The U54-MC Coreplex can be accessed at www.sifive.com/products/coreplex-risc-v-ip/u54-mc. A development board based on U54-MC Coreplex IP will be available in Q1 2018.

www.sifive.com