Startup looks to IoT building blocks to shrink wearable technology: Page 2 of 2

August 23, 2017 // By William Wong
Silicon interposer technology allows multiple die to be combined onto a single chip. This is different from stack or multi-die chips that use wires to connect to a substrate. Essentially, the interposer is similar to a printed circuit board (PCB), but on a much smaller scale.

These include a range of sensors, microcontrollers, memory, and even RF technology like Bluetooth or cellular chiplets. The hybrid memory is used for configuration data, system test support, as well as secure key storage. Memory can also be supplied as a chiplet or as part of other devices like the microcontroller chiplets.

The ZiP platform can employ a number of analog and digital ports—up to 20 of each.

The system also comes with zGlue’s system and power management support. The power management support allows operation with a range of batteries, including lithium and NiCads, as well as low-voltage supplies. Systems have built-in voltage regulators. Eventually gGlue will have a zGlue ZiPlet Store where developers can pick and choose chiplets.

The current configurations provide a working area up to 48mm2 and 20 I/O pins. Standard external interfaces include I2C, SPI, UART, and GPIO. Analog/RF connections up to 2.4 GHz are supported. The interconnect fabric supports up to 3 K connections.

At this point zGlue handles most of the system configuration versus using an FPGA- or PCB-style layout tool. Developers typically come to zGlue with a block diagram or an existing PCB layout that will be converted into a single chip.

It is possible to perform similar tricks found in PCB designs — such as laying out larger spaces for a chiplet — so that larger, typically higher-capacity or -performance chiplets can be utilized in additional products. This is a common methodology when companies need to deliver a range of products with increasing levels of functionality, capacity, or performance.

zGlue’s platform is not a fit for all compact embedded applications, but it can be a significant advantage for those where small, custom configurations are needed. It is significantly less costly than creating a custom SoC while providing similar flexibility when the appropriate chiplets are available.


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