Tiny packaged clock management ICs deliver low jitter

July 18, 2014 // By Graham Prophet
For use in locations such as enterprise networking and storage applications where jitter clock synthesis solution and small form factor are critical, the ZL30250 and ZL30251 flexible clock generators are an ultra-low jitter offering (160 fs [12 kHz to 20 MHz integration band]) in a 5 x 5 mm package capable of replacing multiple high performance crystals and crystal oscillators.

The design platform used on the ZL30250 and ZL30251 is very flexible with highly configurable outputs and offers automatic self-configuration at power-up. This supports up to four different configurations, selected using two device pins. This flexibility includes:

  1. Any-to-any frequency conversion with 0 ppm error (inputs: 10 MHz to 1.25 GHz, outputs: 1 Hz to 1 GHz);
  2. Three universal clock inputs connect to any signal format at any voltage;
  3. Up to three differential outputs, up to six CMOS outputs;
  4. Configurable output signal format and voltage for direct interface without additional components.

The ZL30250 and ZL30251 offer a numerically controlled oscillator (NCO) mode in which output frequencies can be controlled with very high resolution by system software. This capability allows the devices to replace solutions using large, expensive, fixed-frequency voltage-controlled oscillators (VCXOs) with a small, low-cost, any-frequency solution.

The ICs can generate PCI Express (PCIe) clock signals with or without spread-spectrum modulation required in server, storage and communication equipment allowing system designers to comply with EMI requirements. They can be combined with Microsemi's high-performance fan-out buffers to provide complete timing solutions for complex systems. ZL30250 and ZL30251 can accept clock signals from other Microsemi timing ICs, perform frequency conversion and output additional clock signals needed for the system design. These devices are flexible building-blocks that system designers can reuse over and over in various parts of a system design and across multiple designs.