Xilinx Partial Reconfiguration enables dynamic field updates

April 24, 2017 //By Jean-Pierre Joosting
Xilinx has announced the 2017.1 release of the Vivado® Design Suite HLx Editions, with broad availability of Partial Reconfiguration technology to enable dynamic field updates and increased systems integration in a broad range of applications such as wired and wireless networking, test and measurement, aerospace and defense, automotive, and data centers.

Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility of All Programmable devices. System upgradeability and reliability are greatly enhanced by providing the ability to update feature sets in deployed systems, fix bugs, and migrate to new standards while critical functions remain active.

"The use of Partial Reconfiguration in Xilinx devices allowed us to optimize the size of the FPGA, and provide complete flexibility to maintain system connectivity while independently reconfiguring multiple ports in our design," said Craig Palmer, senior engineering manager, Viavi Solutions.

The Partial Reconfiguration technology enables dynamic configurability by swapping portions of the design while the rest remains operational, requiring zero downtime and little impact to cost or development time.

"Partial Reconfiguration of FPGAs is a key element in Keysight's toolbox for creating the next generation of test and measurement solutions. Partial Reconfiguration enables us to manage the ever increasing need for flexibility and complexity of test systems," said Tom Vandeplas, senior researcher, Keysight Laboratories, Keysight Technologies, Inc.

The Vivado Design Suite HLx Editions 2017.1 release is now available for download. Partial Reconfiguration functionality is now included at no additional cost with the Vivado HL Design Edition and HL System Edition.

www.xilinx.com/vivado