More than just RF data converters, the integrated block includes a power-efficient DSP subsystem for flexible configuration and RF signal conditioning. Specifically, the subsystem includes:
- Eight 4 GSPS or sixteen 2 GSPS 12-bit ADCs, with digital down-conversion (DUC);
- Eight to sixteen 6.4 GSPS 14-bit DACs, with digital up-conversion (DDC);
- Direct RF sampling for flexible analog design, greater accuracy, and lower power.
Direct RF sampling, or the ability to sample incoming signals directly without initial down conversion to an intermediate frequency (IF), provides RF designers greater flexibility. Digitizing the signal directly and then applying modern DSP techniques for signal conditioning yields better performance and programmability in the digital domain, particularly on an advanced 16nm FinFET process. To date, direct RF techniques have been incremental in adoption due to the economics and power inefficiency. Though direct RF sampling delivers flexibility in the digital domain, it uses more power as the sample rate rises, has a large footprint due to the use of many discrete components such as DACs and ADCs, and the BOM is large. Monolithically integrating this technology into the SoC itself increases this RF technique’s viability to the broader market. This integration of the RF data converter subsystem by the Zynq RFSoCs delivers lower power through integration, smaller footprint through integration, faster design cycle with less BOM complexity and flexibility in the digital domain.
According to Xilinx, direct RF sampling with Zynq UltraScale+ RFSoCs is easily acieved up to between 4- to 6-GHz depending on the application. Above 6-GHz downsampling is required but there are still the power and size reduction benefits that can be realised in the sub-6-GHz portion of the system.