Xilinx takes RFSoCs to the next level for 5G, cable and radar: Page 3 of 8

October 05, 2017 // By Jean-Pierre Joosting
With silicon shipped to multiple customers already and an early access programin place, Xilinx has announced its Zynq® UltraScale+™ RFSoC family that features a breakthrough architecture integrating the RF signal chain into an SoC for 5G wireless, cable Remote-PHY, and radar.

Critical to the RF signal chain and all communications is forward error correction. This DSP technique corrects signal impairments in data transmission across various transmission mediums such as copper cable, optical fiber, or the air interface. Due to the high throughput requirements of next generation wireless and cable broadband, both the 5G access/backhaul and DOCSIS 3.1 standards require a more compute-intensive FEC coding scheme known as Low Density Parity Check (LDPC) codes in order to maximize spectral efficiency in RF transmission.

While LDPC implementations can range from soft IP in FPGAs to fixed and hardened cores in ASSPs or ASICs, the Zynq UltraScale+ RFSoC balances flexibility, throughput, and power efficiency with the first hardened and fully programmable LDPC encoding/decoding cores in a programmable device.

Capabilities include:

  • Up to 42 Gb/s LDPC encode and 10 Gb/s decode system throughput;
  • Turbo Decode for LTE backward compatibility with 4G LTE-Pro and LTE-Advanced;
  • 80 percent less dynamic power than a soft IP implementation;
  • Flexible, customizable LDPC codes for evolving standards and differentiation;
  • Soft-decision decoding for greater reliability.

With compute-intensive matrix multiplication and continuous read and write to memory, hardening the SD-FEC can meet next generation standards for high throughput systems, such as 5G baseband.

Integrated and fully programmable LDPC codec for 10 to 20X throughput versus soft core.


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.