Critical to the RF signal chain and all communications is forward error correction. This DSP technique corrects signal impairments in data transmission across various transmission mediums such as copper cable, optical fiber, or the air interface. Due to the high throughput requirements of next generation wireless and cable broadband, both the 5G access/backhaul and DOCSIS 3.1 standards require a more compute-intensive FEC coding scheme known as Low Density Parity Check (LDPC) codes in order to maximize spectral efficiency in RF transmission.
While LDPC implementations can range from soft IP in FPGAs to fixed and hardened cores in ASSPs or ASICs, the Zynq UltraScale+ RFSoC balances flexibility, throughput, and power efficiency with the first hardened and fully programmable LDPC encoding/decoding cores in a programmable device.
- Up to 42 Gb/s LDPC encode and 10 Gb/s decode system throughput;
- Turbo Decode for LTE backward compatibility with 4G LTE-Pro and LTE-Advanced;
- 80 percent less dynamic power than a soft IP implementation;
- Flexible, customizable LDPC codes for evolving standards and differentiation;
- Soft-decision decoding for greater reliability.
With compute-intensive matrix multiplication and continuous read and write to memory, hardening the SD-FEC can meet next generation standards for high throughput systems, such as 5G baseband.