Real-time calibration of gain and timing errors in two-channel time-interleaved A/D converters for SDR applications

June 25, 2014 //By Djamel Haddadi, Integrated Device Technology, Inc.
The explosion of mobile data is driving new receiver architectures in communication infrastructure in order to provide higher capacity and more flexibility.

These next generation software defined radio systems are based on power efficient RF A/D converters (RF-ADCs) capable of sampling at the antenna while delivering high dynamic range. Such ADCs are designed in very advanced CMOS technologies using time-interleaved (TIADC) architecture to achieve very high sample rates [1]. This architecture suffers from time-varying mismatch errors [2] that necessitate real-time calibration. This article describes a novel background calibration method for gain and timing mismatch errors through low complexity digital signal processing algorithms.

Mismatch errors in two-channel TIADC

An efficient way to double the speed of an ADC is to operate two ADCs in parallel with out of phase sampling clocks. The unavoidable small mismatches between the transfer functions of the sub-ADCs result in spurious tones that significantly degrade the achievable dynamic range. There are four types of error in this kind of ADC:

  1. DC offset error,
  2. Static gain error,
  3. Timing error,
  4. Bandwidth error.

The DC offset error is very simple to handle in practice through digital calibration. The bandwidth error is the most difficult to manage and it is usually mitigated through careful design and layout. In this article we will focus on gain and timing error calibration as they are the major contributors to dynamic range loss.

Design category: