The Chiplet Alternative
Figure 3 shows a comparable architecture as that shown in Figure 2 but reconfigured with a chiplet based approach. In this case, a higher bandwidth, lower latency and lower power interface is used to connect the CPU SoC die with a look-aside hardware acceleration FPGA chiplet. The FPGA device supporting the fronthaul connection to the Radio Unit is not package integrated in this example but could be; indeed, it could be the same device chiplet as the hardware acceleration chiplet, if there are sufficient resources.
The two primary techniques for package integration are with a silicon interposer or with an organic substrate and some form of Ultra-Short Reach (USR) transceiver.
A fully integrated 5G vision
Finally, Figure 4 shows the final, most integrated, architecture for baseband considered here. This approach includes the same processing elements as previously, with the same functionality, but with embedded FPGA monolithically integrated on the die.
This tightly integrated approach of monolithic integration has a number of benefits. This interface has higher bandwidth, lower latency and lower energy-per-bit than that observed in a chiplet based approach. Moreover, the resource mix can be tailored to the specific application under consideration and therefore unwanted interfaces, memory and core logic is avoided. This also results in the lowest unit cost of the three architectures under consideration.