The availability of complete 3GPP-compliant channel coding chains optimised for implementation in software-only, FPGA or ASIC platforms will enable AccelerComm’s customers to accelerate 5G technology developments while maximising spectrum efficiency through excellent block error rate (BLER) performance.
AccelerComm’s CTO, Professor Rob Maunder, commented: “Flexibility is key to success when developing advanced communications and these high performance standardized architectures in the wireless infrastructure market are enabling that flexibility while helping to reduce development time."
AccelerComm’s offering is compliant with the 5G NR specification set by 3GPP and covers the encode/decode engine, channel interleaving, rate matching, and cyclical redundancy check.
The processing performance is up to 2.5 times higher than the Intel SCL decoder core provided in the FlexRAN SDK, and offers up to 0.3dB improved BLER performance.
AccelerComm has demonstrated its polar coding software running on an Intel X-Series processor and a variety of Intel and Xilinx FPGAs.
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