The Gen4 CEVA-XC DSP architecture delivers unmatched performance for the most complex parallel processing workloads required for 5G endpoints and RAN, enterprise access points and other multigigabit low latency applications.
The Gen4 CEVA-XC unifies the principles of scalar and vector processing in a powerful architecture, enabling two-times 8-way VLIW and up to an unprecedented 14,000 bits of data level parallelism. It incorporates an advanced, deep pipeline architecture enabling operating speeds of 1.8 GHz at a 7nm process node using a unique physical design architecture for a fully synthesizable design flow, and an innovative multithreading design. This allows the processors to be dynamically reconfigured as either a wide SIMD machine or divided into smaller simultaneous SIMD threads. This architecture also features a novel memory subsystem, using 2048-bit memory bandwidth, with coherent, tightly-coupled memory to support efficient simultaneous multithreading and memory access.
Mike Demler, Senior Analyst at The Linley Group, commented: “The Gen4 CEVA-XC architecture demonstrates CEVA’s industry-leading commitment to driving DSP innovation forward for parallel processing. Its dynamically reconfigurable multithreading and high speed design, along with comprehensive capabilities for both control and arithmetic processing, sets the foundation for the proliferation of ASICs and ASSPs for 5G infrastructure and endpoints.”