This chipset enables 200G modules at under 4.5 W and 400G modules at under 9 W total power consumption, thus delivering industry-leading power efficiency with a fully analog architecture that ensures extremely low latency and is poised to provide a lower cost option compared to DSP-based offerings.
The full transmit and receive chipset operates at up to 53 Gbps PAM-4 data rates per lane and is optimized for use in 200G QSFP56 and 400G QSFP-DD and OSFP module applications. For the 200G demonstration at ECOC 2018 in Rome, the system is comprised of the MAOM-38051 four-channel transmit CDR and modulator driver and MAOT-025402 TOSA with embedded MAOP-L284CN CWDM L-PIC™ (silicon photonic integrated circuit with integrated CW lasers) transmitter, and on the receive side features the MAOR-053401 ROSA with embedded demultiplexer, BSP56B photodetectors MATA-03819 quad TIA and the MASC-38040 four-channel receive CDR. The combined, high-performance MACOM system enables a low bit error rate (BER) and better than 1E-8 pre-forward error correction (Pre-FEC).
“MACOM is committed to leading the evolution of Data Center interconnects from 100G to 200G and 400G, as evidenced by our unique ability to deliver a complete 200G chipset and TOSA/ROSA subassembly solution with market leading performance and power efficiency,” said Gary Shah, Vice President, High-Performance Analog Business Line, MACOM. “With this solution, optical module providers are expected to benefit from seamless component interoperability and a unified support team, reducing design complexity and costs while accelerating their time to market.”
All of the MACOM products highlighted in the forthcoming 200G live demonstrations are sampling to customers today, with production availability targeted for early 2019. Customers can select from component-level products or a TOSA/ROSA subassembly-level system.
The European Conference on Optical Communication (ECOC) will take place in Rome, Italy, September 24th – 26th.