Tiny all-digital PLL opens doors to 5 nm semiconductors : Page 2 of 3

February 11, 2020 //By Jean-Pierre Joosting
Tiny all-digital PLL opens doors to 5 nm semiconductors
Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext claim to have designed the smallest all-digital phase-locked loop (PLL), a key step in the race to develop increasingly smaller semiconductors down to 5nm node.

Okada and team used several techniques to decrease the required area, power consumption and jitter—unwanted time fluctuations when transmitting digital signals—of their synthesizable PLLs. To decrease area, they employed a ring oscillator, a compact oscillator that can be easily scaled down. To suppress jitter, they reduced the phase noise—random fluctuations in a signal—of this ring oscillator, using 'injection locking'—the process of synchronizing an oscillator with an external signal whose frequency (or multiple of it) is close to that of the oscillator—over a wide range of frequencies. The lower phase noise, in turn, reduced power consumption.

The design of this synthesizable PLL beats that of all other current state-of-the-art PLLs in many important aspects. It achieves the best jitter performance with the lowest power consumption and smallest area. "The core area is 0.0036 mm2, and the whole PLL is implemented as one layout with a single power supply," remarks Okada. Further, it can be built using standard digital design tools, allowing for its rapid, low-effort, and low-cost production, making it commercially viable.

This synthesizable PLL can be easily integrated into the design of all-digital SoCs, and is commercially viable, making it valuable for developing the much sought after 5 nm semiconductor for cutting-edge applications including artificial intelligence, internet of things and many others, where high performance and low power consumption would be the critical requirements. But the contributions of this research go beyond these possibilities.

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