Tiny all-digital PLL opens doors to 5 nm semiconductors : Page 3 of 3

February 11, 2020 //By Jean-Pierre Joosting
Tiny all-digital PLL opens doors to 5 nm semiconductors
Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext claim to have designed the smallest all-digital phase-locked loop (PLL), a key step in the race to develop increasingly smaller semiconductors down to 5nm node.

"Our work demonstrates the potential of synthesizable circuits. With the design methodology employed here, other building blocks of SoCs, such as data converters, power management circuits, and wireless transceivers, could be made synthesizable as well. This would greatly boost design productivity and considerably reduce design efforts," explains Okada. Tokyo Tech and Socionext will continue their collaboration in this field to advance the miniaturization of electronic devices, enabling the realization of newer-generation technologies.

This research work was conducted in cooperation with TeraPixel Technologies Inc.

www.titech.ac.jp/english
www.socionext.com


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